The present invention relates to a solid-state image sensor and a method for manufacturing thereof as well as a semiconductor device and a method for manufacturing thereof, in which a semiconductor substrate needs to be a thin film.
Description of the Related Art
A CMOS solid-state image sensor that designates an X-Y address to be read out and a CCD solid-state image sensor that is a charge transfer type are typical as a solid-state image sensor. In each of the solid-state image sensors, photoelectric conversion is performed on incident light into a photodiode two-dimensionally arranged and one of the electric charges (for example, electron) is made to be a signal electric charge.
With respect to the CMOS solid-state image sensor, a CMOS solid-state image sensor of a front-illuminated type in which light is illuminated from the front surface side where a wiring layer of a semiconductor substrate is formed and the light is detected by a photodiode formed on the semiconductor substrate is typical. However, in this CMOS solid-state image sensor of the front-illuminated type, it is known that efficiency in using light is reduced and sensitivity is lowered, because multi-layered wirings exist on the route of light illuminated, particularly, on the optical path of oblique light in the vicinity of the effective pixel area and the light is scattered by the multi-layered wirings. Because of this, a CMOS solid-state image sensor of a back-illuminated type is promising in which light is illuminated from the rear side of a semiconductor substrate where the multi-layered wirings are formed on the front surface side (refer to Patent Document 1).
Further, in the CCD solid-state image sensor, it is known that light is absorbed into an interlayer insulation layer on the element to reduce sensitivity and so a structure where light is illuminated from the rear side of the substrate to perform photoelectric conversion has been proposed (refer to Patent Document 2).
Patent Document 1: Published Japanese Patent Application No. 2003-31785
Patent Document 2: Published Japanese Patent Application No. H6-29506
As for a CMOS solid-state image sensor, for example, in the case where light is illuminated from the rear side of the substrate, because typically the thickness of a silicon substrate is thick such as several hundred μm not to pass the light, it is necessary to make the silicon substrate thin to be 10 μm or less. If the film thickness of the silicon layer is uneven when making a thin film, differences in the strength of incident light are caused and such inconvenience as unevenness with respect to color occurs.
On the other hand, a method using an SOI (Silicon On Insulator) substrate has been considered to prevent unevenness of the film thickness of the silicon layer. In other words, by using the SOI substrate, mechanical polishing of a high speed etching rate is applied, then CMP (Chemical Mechanical Polishing) processing is applied, and wet etching is applied and with operation of making thin film being stopped at a SiO2 layer, unevenness of the film thickness of the silicon layer is prevented.
A method for manufacturing a CMOS solid-state image sensor of the back-illuminated type using the SOI substrate is explained referring to FIGS. 1 through 3.
First, as shown in FIG. 1A, an SOI substrate 4 in which a thin-film silicon layer 3 is formed on a silicon substrate 1 with a silicon oxide film (SiO2 film) 2 in between is prepared. An alignment mark 5 is formed at a required position in the silicon layer 3 of this SOI substrate 4.
Next, as shown in FIG. 1B, with the alignment mark 5 used as a reference, in the silicon layer 3 from the front surface side are formed a pixel separation area in an image area (not shown), a semiconductor well area (not shown), a photodiode PD to be a photoelectric conversion element and a plurality of MOS transistors of a HAD (Hole Accumulation Diode) structure which constitute a pixel with the photodiodes PD.
Further, a multi-layered wiring layer 6 is laminated thereon in which a multi-layer wiring 8 is formed with an interlayer insulation layer 7 in between.
Next, as shown in FIG. 2A, for example, a support substrate 9 such as a silicon substrate or the like is stuck to the multi-layered wiring layer 6.
Then, as shown in FIG. 2B, the SOI substrate 4 is reversed, and the silicon substrate 1 is polished and removed by back-grinding (mechanical rough grinding) and wet-etching with the silicon oxide film 2 being used as a stopper film. Further, the silicon oxide film 2 is removed by the wet-etching.
Next, as shown in FIG. 3A, for example, a silicon nitride film 10 to be a passivation film is formed on the rear surface of the silicon layer 3, and an opening 11 that reaches a wiring layer 8a is formed by selectively etching part of the silicon layer 3 together with the silicon nitride film 10, namely at a portion where an electrode should be derived from the wiring layer 8a. Further, for example, an insulation film 12 such as a silicon oxide film is formed from the inside wall of the opening 11 to cover the surface of the silicon nitride film 10. A conductive layer 13 that connects to the wiring layer 8a inside the opening 11 is formed and an electrode pad 14 that connects to the conductive layer 13 and faces to the rear surface is formed, and what is called a rear surface electrode 15 is formed.
Next, as shown in FIG. 3B, a color filter 16 and an on-chip lens 17 are formed on the rear surface at a position corresponding to the photodiode PD of each pixel, and a CMOS solid-state image sensor of the back-illuminated type 18 is obtained.
However, in the case where the CMOS solid-state image sensor of the back-illuminated type is manufactured using the SOI substrate, there has been a problem that the manufacturing cost increases because the cost of the SOI substrate is higher than that of a silicon substrate.
The problem when using such an SOI substrate also occurs in a CCD solid-state image sensor of the back-illuminated type, and furthermore, not limited to the solid-state image sensor, the problem may also occur, for example, in a semiconductor circuit device in which a semiconductor element and/or multi-layered wiring are formed on both the front and rear surfaces of a semiconductor substrate.